1. Field of the Present Invention
The present invention generally relates to the field of data processing systems and more particularly to a system and method for addressing processor-based systems that are connected to a common peripheral bus.
2. History of Related Art
In the field of data processing systems, the use of standardized peripheral or IO busses is well known. Among the more prevalent of such busses is the Peripheral Components Interface (PCI) bus as specified in the PCI Local Bus Specification Rev. 2.2 available from the PCI Special Interest Group 5440 SW Westgate Drive, Suite 217, Portland, Oreg. 97221. All devices connected to a PCI bus are mapped into a common, shared address space. Any bus master or transaction initiator can access any target device simply by reading or writing the target""s portion of the shared address space. PCI transactions are said to be anonymous because target devices are unable to determine the initiator of a transaction. The shared, anonymous characteristics of PCI are generally desirable attributes for conventional PCI environments in which a CPU or set of CPUs is one of the bus agents and the computer system peripherals are the other bus agents.
Referring to FIG. 3, a data processing system 300 typical of the prior art is depicted. Data processing system 300 includes one or more processors 302 that are each connected to a system bus 303. Processors 302 can access a system memory 304 via the system bus 303. In addition, a bus controller/bus arbiter 306 is connected between the system bus 303 and a peripheral bus 307. For purposes of this discussion, the peripheral bus 307 is typically compliant with Rev. 2.2 of the PCI Local Bus specification. One or more peripheral device(s) or adapter(s) 308 are connected to the peripheral bus 307. Peripheral devices 308 may include any number of devices including, as examples, hard disk adapters, graphics adapters, audio adapters, and high-speed network adapters. The address space of bus 307 is divided among peripheral devices 308. Typically, each peripheral device 308 tied to peripheral bus 307 is able to xe2x80x9cseexe2x80x9d every transaction that occurs on the bus. More specifically, all devices 308 on bus 307 receive the same data, address, and control signals. Thus, bus 307 is referred to as a shared bus. In addition, transactions on bus 307 are anonymous because the data, address, and control signals of bus 307 typically do not include information indicating the device that originated the transaction.
While a common, shared address space may be suitable for traditional microprocessor-based designs, it may be undesirable in a PCI-based multiprocessor environment. For purposes of this disclosure, a PCI-based multiprocessing system refers to a computer system in which multiple CPU-based systems are connected to a single PCI bus, typically through a backplane connection. In this environment, it may be desirable to isolate selected processors from others and to enable xe2x80x9cprivate conversationsxe2x80x9d between processors or between one or more processors and selected peripherals. The shared address space and anonymous transactions of the currently implemented PCI make it difficult for each processor to communicate to its counterparts on the bus. It would, therefore, be highly desirable to implement a system and method for enabling processors on a common PCI bus to communicate with each other. It would be further desirable if the implemented system did not require modification of existing PCI compliant devices and did not require alteration or amendment of the PCI specification itself. It would be still further desirable if the implemented solution did not require complex or extensive modifications to existing hardware.
The problems identified above are in large part addressed by a system and method in which two or more processors are connected together on a common peripheral bus such as a PCI bus. Each of the processors may communicate with the peripheral bus through an intermediate bus controller. The bus controller may include facilities, such as a register that defines a starting address, suitable for defining a window in its corresponding system memory that is available or visible to other processors (or masters) on the PCI bus. These facilities for defining the visible window in memory space may include existing facilities designed for defining a graphics memory window in system memory, such as facilities found in processors implementing the Accelerated Graphics Port (AGP) protocol.
One or more of the bus controllers may be configured to read information that uniquely identifies each system or blade. The bus controller may use this identification information to define the window in the blade""s system memory that is visible or available to other processors or bus masters. In an embodiment where each blade is connected to a PCI bus through a CompactPCI(copyright) connector, for example, the identification information may be read from the geographic address (GA) pins on the system""s J2 connector, where each blade""s GA pins are hardwired to a unique combination of 0""s (ground) and 1""s Vcc at the connector.
In one embodiment, the system may include a system server blade that determines the number of server blades connected to the bus and the identification information associated with each connected blade. The system server blade may provide this information to each connected blade on the bus such that each system is aware of the other systems connected to the bus. Alternatively, each processor can scan the bus testing predetermined memory address ranges to identify other bus participants.
By using information that is unique to each blade on the bus to define the memory window that is accessible to each system, the invention enables the use of unique memory spaces on each processor target without introducing address mapping hardware that might otherwise be required.